The present invention relates generally to packaging semiconductor devices and, more particularly, the present invention relates to fine ball grid array packages that can be stacked to form highly dense components.
Ball grid array (BGA) semiconductor packages are well known in the art. BGA packages typically comprise a substrate, such as a printed circuit board, with a semiconductor die mounted on the top side of the substrate. The semiconductor die has a multitude of bond pads electrically connected to a series of metal traces on the top side of the printed circuit board. The connection between the bond pads and the metal traces is provided by wire bonds electrically and mechanically connected between the two. This series of metal traces is connected to a second series of metal traces on the underside of the printed circuit board through a series of vias. The second series of metal traces each terminate with a connect contact pad where a conductive element is attached. The conductive elements can be solder balls or conductive filled epoxy. The conductive elements are arranged in an array pattern and the semiconductor die and wire bonds are encapsulated with a molding compound.
As chip and grid array densities increase, the desire in packaging semiconductor chips has been to reduce the overall height or profile of the semiconductor package. The use of BGAs has allowed for this reduction of profile as well as increased package density. Density reduction has been achieved by utilizing lead frames, such as lead-over chips, in order to increase the densities as well as to branch out into being able to stack units one on top another.
One example of a lead chip design in a BGA package is shown in U.S. Pat. 5,668,405, issued Sep. 16, 1997. This patent discloses a semiconductor device that has a lead frame attached to the semiconductor chip. Through holes are provided that allow for solder bumps to connect via the lead frame to the semiconductor device. This particular reference requires several steps of attaching the semiconductor device to the lead frame, then providing sealing resin, and then adding a base film and forming through holes in the base film. A cover resin is added before solder bumps are added in the through holes to connect to the lead frame. This particular structure lacks the ability to stack devices one on top another.
U.S. Pat. 5,677,566, issued Oct. 14, 1997, and commonly assigned to the assignee of the present invention, discloses a semiconductor chip package that includes discrete conductive leads with electrical contact bond pads on a semiconductor chip. The lead assembly is encapsulated with a typical encapsulating material and electrode bumps are formed through the encapsulating material to contact the conductive leads. The electrode bumps protrude from the encapsulating material for connection to an external circuit. The semiconductor chip has the bond leads located in the center of the die, thus allowing the conductive leads to be more readily protected once encapsulated in the encapsulating material. Unfortunately, this particular assembly taught in the 566 patent reference also lacks the ability to stack one semiconductor device on top another.
Attempts have been made to stack semiconductor devices in three dimensional integrated circuit packages. One such design is disclosed in U.S. Pat. 5,625,221, issued Apr. 29, 1997. This patent discloses a semiconductor package assembly that has recessed edge portions that extend along at least one edge portion of the assembly. An upper surface lead is exposed therefrom and a top recess portion is disposed on a top surface of the assembly. A bottom recess portion is disposed on the bottom surface of the assembly such that when the assembly is used in fabricating a three-dimensional integrated circuit module, the recessed edge portion accommodates leads belonging to an upper semiconductor assembly to provide electrical interconnection therebetween. Unfortunately, the assembly requires long lead wires from the semiconductor chip to the outer edges. These lead wires add harmful inductance and unnecessary signal delay and can form a weak link in the electrical interconnection between the semiconductor device and the outer edges. Further, the device profile is a sum of the height of the semiconductor die, the printed circuit board to which it is bonded, the conductive elements, such as the solder balls, and the encapsulant that must cover the die and any wire bonds used to connect the die to the printed circuit board. So, reducing the overall profile is difficult because of the geometries required in having the lead pads on the semiconductor chip along the outer periphery with extended lead wires reaching from the chip to the outer edges.
Another stacked arrangement of semiconductor devices on a substrate interconnected by pins is illustrated in U.S. Pat. No. 5,266,912 and 5,400,003. However, the height of the stacked package is limited by the length of the pin connections between the individual multi-chip modules or printed circuit boards.
Accordingly, what is needed is a ball grid array package that allows stacking of packages on one another. This stackable package would have a lower profile than otherwise provided in the prior art and would reduce the number of steps in the assembly of the package.
According to the present invention, a stackable fine ball grid array (FBGA) package is disclosed that allows the stacking of one array upon another. This stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of a semiconductor device (integrated circuit (IC) device) mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device. Wire interconnect connects the IC device in a way that does not increase the overall profile of the package. Encapsulating material protects both the IC device and the wire interconnect as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires, or wire interconnect, are used to attach the IC device to the printed circuit board substrate and an encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.
Additionally, certain pins on the FBGA in the stack require an isolated connection to the PC board. An example of such a requirement is when an activation signal for a particular IC device within the stack must be sent solely to that device and not to any of the other devices within the stack. This isolated connection connects to an adjacent ball on a different FBGA stack above or below that particular isolated connection since in common pin layouts of the devices are stacked together, and each device requires an isolated connection to the PC board. This provides for a stair step connection from the bottom of the FBGA stacked array to the top that allows each device, from the bottom one to the top one, to have an isolated connection from each other. This allows IC devices to be stacked one upon the other while maintaining a unique pin out for each pin required in the stack.
Further, the FBGA of the present invention keeps the wire lengths between the IC device and the conductors of the PC board to a minimum for the control of the impedance of the conductors.